This invention relates to the field of power amplifiers. More particularly, this invention relates to improved power amplifier circuitry which reduces the peak voltages to which switching devices of the amplifier are subjected.
In some applications utilizing a power amplifier, it is desirable to limit the peak voltage that the switching devices of the power amplifier are subjected to. For example, in CMOS devices, the transistor breakdown voltage may be only slightly greater than the supply voltage. Therefore, CMOS devices are not well suited to traditional power amplifier designs, where switching devices are subjected to voltages at least twice the supply voltage.
FIG. 1 is a schematic diagram of a conventional Class E amplifier. As shown, a transistor M1 is connected between ground and an inductor L1 which is connected to a voltage source Vdd. The gate of the transistor M1 is connected to an input signal Vi. The connection of the transistor M1 and the inductor L1 forms a node labeled Vd. The switching device M1, as well as other switching devices described may be comprised of any suitable switching devices, for example, MOSFETs or other transistor types. A capacitor C1 is connected between Vd and ground. The amplifier includes a transformation network consisting of inductor L2 and capacitor C2. The capacitor C2 is connected to a load RL at output node Vo.
FIG. 2 is a timing diagram illustrating the input signal Vi and the resulting voltage at Vd. As shown, the input signal Vi is a square wave signal switching between ground and Vdd. When the input signal Vi is high (Vdd), the transistor M1 is turned on, holding Vd to ground. When the input signal Vi transitions to low, transistor M1 turns off and the voltage at Vd rises above Vdd. During this time, the transistor M1 must sustain this high drain-to-source voltage. After peaking, the voltage at Vd decreases until it reaches ground. In a typical prior art Class E design, this peak voltage is approximately 3.6 Vdd. Although the peak voltage can be reduced slightly, it can not be decreased below about 2.5 Vdd since the average voltage at Vd must equal Vdd. Designs such as that shown in FIG. 1 are not well suited to certain device technologies, such as CMOS, where transistor breakdown voltages are only slightly higher than the supply voltage.
It can therefore be seen that there is a need for amplifier designs where the peak voltages applied to the transistors of the amplifier are reduced so that they are below the transistor breakdown voltages of the devices being used to implement the design.
Another problem relating to amplifiers relates to the use of differential circuits. It is difficult to perform differential-to-single-ended conversion when a single ended load is required with high efficiency. Therefore, there is a need for improved differential-to-single-ended conversion designs.
A power amplifier of the invention includes a first switching device connected between a first supply voltage and a first output node, a second switching device connected between a second supply voltage and a second output node, and an inductance coupled between the first and second output nodes.
Another embodiment of the invention provides a method of reducing the peak output voltage in an amplifier including the steps of providing an inductor having first and second terminals, providing a first switching device connected between the first terminal of the inductor and a first supply voltage, providing a second switching device connected between the second terminal of the inductor and a second supply voltage, applying a voltage between the first and second terminals of the inductor during a first portion of a clock cycle by turning on the first and second switching devices, and turning off the first and second switching devices during a second portion of the clock cycle.
Another embodiment of the invention provides a differential power amplifier including a first amplifier having a first switching device connected between a first supply voltage and a first output node, a second switching device connected between a second supply voltage and a second output node, and an inductance coupled between the first and second output nodes, a second amplifier having a third switching device connected between a third supply voltage and a third output node, a fourth switching device connected between a fourth supply voltage and a fourth output node, and an inductance coupled between the third and fourth output nodes, and wherein the first and second amplifiers are coupled together to drive a load.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.